Non-volatile memory with optimized operation sequence

ABSTRACT

A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.

This application is a continuation-in-part of U.S. patent application Ser. No. 17/873,617, titled “Non-Volatile Memory With Optimized Erase Verify Sequence,” filed on Jul. 26, 2022, which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to non-volatile storage.

Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). One example of non-volatile memory is flash memory (e.g., NAND-type and NOR-type flash memory).

Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read that data back. For example, a digital camera may take a photograph and store the photograph in non-volatile memory. Later, a user of the digital camera may view the photograph by having the digital camera read the photograph from the non-volatile memory. It is important that the processes performed by non-volatile memory be fast so that users do not have to wait very long for the non-volatile memory to finish tasks.

BRIEF DESCRIPTION OF THE DRAWINGS

Like-numbered elements refer to common components in the different figures.

FIG. 1 is a block diagram depicting one embodiment of a storage system.

FIG. 2A is a block diagram of one embodiment of a memory die.

FIG. 2B is a block diagram of one embodiment of an integrated memory assembly.

FIGS. 3A and 3B depict different embodiments of integrated memory assemblies.

FIG. 4 is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

FIG. 4A is a block diagram of one embodiment of a memory structure having two planes.

FIG. 4B depicts a top view of a portion of one embodiment of a block of memory cells.

FIG. 4C depicts a cross sectional view of a portion of one embodiment of a block of memory cells.

FIG. 4D depicts a cross sectional view of a portion of one embodiment of a block of memory cells.

FIG. 4E is a cross sectional view of one embodiment of a vertical column of memory cells.

FIG. 4F is a schematic of a plurality of NAND strings in multiple sub-blocks of a same block.

FIG. 5A depicts threshold voltage distributions.

FIG. 5B depicts threshold voltage distributions.

FIG. 5C depicts threshold voltage distributions.

FIG. 5D depicts threshold voltage distributions.

FIG. 6 is a flow chart describing one embodiment of a process for programming non-volatile memory.

FIG. 7 depicts the erasing of a NAND string.

FIG. 8 is a flow chart describing one embodiment of a process for erasing.

FIG. 9 is a flow chart describing one embodiment of a process for erasing.

FIG. 10 is a table indicating various values for a parameter used to configure erase verify.

FIG. 11 is a flow chart describing one embodiment of a process for erasing.

FIG. 12 is a flow chart describing one embodiment of a process for erasing.

FIG. 13 is a flow chart describing one embodiment of a process for performing a memory operation.

FIGS. 14A and 14B are tables that explain a process for verifying programming of memory cells.

FIG. 15 is a flow chart describing one embodiment of a process for programming.

FIG. 16 is a table indicating various values for a parameter used to configure programming.

FIG. 17 is a block diagram depicting four planes of memory.

FIG. 18 is a table depicting an order of programming.

FIG. 19 is a table depicting an order of programming.

DETAILED DESCRIPTION

A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process, thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.

One embodiment includes determining speed of programming for multiple sub-blocks relative to each other; configuring order of programming the multiple sub-blocks from slower sub-block to faster sub-block; and concurrently programming memory cells in multiple planes to a data state including programming data into multiple subs-blocks of blocks in the configured order of programming from slower sub-block to faster sub-block. The process includes using completion of programming of a fastest plane to the data state as a trigger to test for program failure of other planes to the data state. The test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming after completion of programming of the fastest plane to the data state. The process further includes aborting the programming for a respective plane prior to completion of programming for all of the sub-blocks of the block in the respective plane in response to determining that any sub-block of the block in the respective plane failed programming based on the test for program failure.

FIG. 1 is a block diagram of one embodiment of a storage system 100 that implements the proposed technology described herein. In one embodiment, storage system 100 is a solid state drive (“SSD”). Storage system 100 can also be a memory card, USB drive or other type of storage system. The proposed technology is not limited to any one type of memory system. Storage system 100 is connected to host 102, which can be a computer, server, electronic device (e.g., smart phone, tablet or other mobile device), appliance, or another apparatus that uses memory and has data processing capabilities. In some embodiments, host 102 is separate from, but connected to, storage system 100. In other embodiments, storage system 100 is embedded within host 102.

The components of storage system 100 depicted in FIG. 1 are electrical circuits. Storage system 100 includes a memory controller 120 connected to non-volatile memory 130 and local high speed volatile memory 140 (e.g., DRAM). Local high speed volatile memory 140 is used by memory controller 120 to perform certain functions. For example, local high speed volatile memory 140 stores logical to physical address translation tables (“L2P tables”).

Memory controller 120 comprises a host interface 152 that is connected to and in communication with host 102. In one embodiment, host interface 152 implements a NVM Express (NVMe) over PCI Express (PCIe). Other interfaces can also be used, such as SCSI, SATA, etc. Host interface 152 is also connected to a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit. NOC's can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications and brings notable improvements over conventional bus and crossbar interconnections. NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and the links of the NOC are shared by many signals. A high level of parallelism is achieved because all links in the NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems keep growing, a NOC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, NOC 154 can be replaced by a bus. Connected to and in communication with NOC 154 is processor 156, ECC engine 158, memory interface 160, and DRAM controller 164. DRAM controller 164 is used to operate and communicate with local high speed volatile memory 140 (e.g., DRAM). In other embodiments, local high speed volatile memory 140 can be SRAM or another type of volatile memory.

ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding, as per the implemented ECC technique. In one embodiment, ECC engine 158 is an electrical circuit programmed by software. For example, ECC engine 158 can be a processor that can be programmed. In other embodiments, ECC engine 158 is a custom and dedicated hardware circuit without any software. In another embodiment, the function of ECC engine 158 is implemented by processor 156.

Processor 156 performs the various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom and dedicated hardware circuit without any software. Processor 156 also implements a translation module, as a software/firmware process or as a dedicated hardware circuit. In many systems, the non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory die. To implement this system, memory controller 120 (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies. One example implementation is to maintain tables (i.e., the L2P tables mentioned above) that identify the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word “tables” they need not literally be tables. Rather, the logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of a storage system is so large that the local memory 140 cannot hold all of the L2P tables. In such a case, the entire set of L2P tables are stored in a memory die 130 and a subset of the L2P tables are cached (L2P cache) in the local high speed volatile memory 140.

Memory interface 160 communicates with non-volatile memory 130. In one embodiment, memory interface provides a Toggle Mode interface. Other interfaces can also be used. In some example implementations, memory interface 160 (or another portion of controller 120) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory die.

In one embodiment, non-volatile memory 130 comprises one or more memory die. FIG. 2A is a functional block diagram of one embodiment of a memory die 200 that comprises non-volatile memory 130. Each of the one or more memory die of non-volatile memory 130 can be implemented as memory die 200 of FIG. 2A. The components depicted in FIG. 2A are electrical circuits. Memory die 200 includes a memory structure 202 that can comprises non-volatile memory cells, as described in more detail below. The array terminal lines of memory structure 202 include the various layer(s) of word lines organized as rows, and the various layer(s) of bit lines organized as columns. However, other orientations can also be implemented. Memory die 200 includes row control circuitry 220, whose outputs 208 are connected to respective word lines of the memory structure 202. Row control circuitry 220 receives a group of M row address signals and one or more various control signals from System Control Logic circuit 260, and typically may include such circuits as row decoders 222, array terminal drivers 224, and block select circuitry 226 for both reading and writing (programming) operations. Row control circuitry 220 may also include read/write circuitry. Memory die 200 also includes column control circuitry 210 including sense amplifier(s) 230 whose input/outputs 206 are connected to respective bit lines of the memory structure 202. Although only single block is shown for memory structure 202, a memory die can include multiple arrays that can be individually accessed. Column control circuitry 210 receives a group of N column address signals and one or more various control signals from System Control Logic 260, and typically may include such circuits as column decoders 212, array terminal receivers or driver circuits 214, block select circuitry 216, as well as read/write circuitry, and I/O multiplexers.

System control logic 260 receives data and commands from memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which comprises one or more electrical circuits) include state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 is programmable by software. In other embodiments, the state machine 262 does not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, the state machine 262 is replaced by a micro-controller or microprocessor, either on or off the memory chip. System control logic 262 can also include a power control module 264 that controls the power and voltages supplied to the rows and columns of the memory structure 202 during memory operations and may include charge pumps and regulator circuit for creating regulating voltages. System control logic 262 includes storage 366 (e.g., RAM, registers, latches, etc.), which may be used to store parameters for operating the memory structure 202.

Commands and data are transferred between memory controller 120 and memory die 200 via memory controller interface 268 (also referred to as a “communication interface”). Memory controller interface 268 is an electrical interface for communicating with memory controller 120. Examples of memory controller interface 268 include a Toggle Mode Interface and an Open NAND Flash Interface (ONFI). Other I/O interfaces can also be used.

In some embodiments, all the elements of memory die 200, including the system control logic 260, can be formed as part of a single die. In other embodiments, some or all of the system control logic 260 can be formed on a different die.

In one embodiment, memory structure 202 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping layers.

In another embodiment, memory structure 302 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used.

The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure 202 include ReRAM memories (resistive random access memories), magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure 202 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.

One example of a ReRAM cross-point memory includes reversible resistance-switching elements arranged in cross-point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.

Another example is magnetoresistive random access memory (MRAM) that stores data by magnetic storage elements. The elements are formed from two ferromagnetic layers, each of which can hold a magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity; the other layer's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created. MRAM based memory embodiments will be discussed in more detail below.

Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses. Note that the use of “pulse” in this document does not require a square pulse but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave. These memory elements within the individual selectable memory cells, or bits, may include a further series element that is a selector, such as an ovonic threshold switch or metal insulator substrate.

A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, memory construction or material composition, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

The elements of FIG. 2A can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuitry, which includes all of the other components depicted in FIG. 2A. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of the memory die of storage system 100 that is given over to the memory structure 202; however, this reduces the area of the memory die available for the peripheral circuitry. This can place quite severe restrictions on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuits within the available area can be a significant restriction on sense amplifier design architectures. With respect to the system control logic 260, reduced availability of area can limit the available functionalities that can be implemented on-chip. Consequently, a basic trade-off in the design of a memory die for the storage system 100 is the amount of area to devote to the memory structure 202 and the amount of area to devote to the peripheral circuitry.

Another area in which the memory structure 202 and the peripheral circuitry are often at odds is in the processing involved in forming these regions, since these regions often involve differing processing technologies and the trade-off in having differing technologies on a single die. For example, when the memory structure 202 is NAND flash, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 260 often employ PMOS devices. Processing operations for manufacturing a CMOS die will differ in many aspects from the processing operations optimized for an NMOS flash NAND memory or other memory cell technologies.

To improve upon these limitations, embodiments described below can separate the elements of FIG. 2A onto separately formed dies that are then bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die) and some or all of the peripheral circuitry elements, including one or more control circuits, can be formed on a separate die (referred to as the control die). For example, a memory die can be formed of just the memory elements, such as the array of memory cells of flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all of the peripheral circuitry, even including elements such as decoders and sense amplifiers, can then be moved on to a separate control die. This allows each of the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS based memory array structure, without worrying about the CMOS elements that have now been moved onto a control die that can be optimized for CMOS processing. This allows more space for the peripheral elements, which can now incorporate additional capabilities that could not be readily incorporated were they restricted to the margins of the same die holding the memory cell array. The two die can then be bonded together in a bonded multi-die memory circuit, with the array on the one die connected to the periphery elements on the other die. Although the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments can use more die, such as two memory die and one control die, for example.

FIG. 2B shows an alternative arrangement to that of FIG. 2A which may be implemented using wafer-to-wafer bonding to provide a bonded die pair. FIG. 2B depicts a functional block diagram of one embodiment of an integrated memory assembly 207. One or more integrated memory assemblies 207 may be used to implement the non-volatile memory 130 of storage system 100. The integrated memory assembly 207 includes two types of semiconductor die (or more succinctly, “die”). Memory die 201 includes memory structure 202. Memory structure 202 includes non-volatile memory cells. Control die 211 includes control circuitry 260, 210, and 220 (as described above). In some embodiments, control die 211 is configured to connect to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

FIG. 2B shows an example of the peripheral circuitry, including control circuits, formed in a peripheral circuit or control die 211 coupled to memory structure 202 formed in memory die 201. Common components are labelled similarly to FIG. 2A. System control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of the column control circuitry 210 and all or a portion of the row control circuitry 220 are located on the memory die 201. In some embodiments, some of the circuitry in the system control logic 260 is located on the on the memory die 201.

System control logic 260, row control circuitry 220, and column control circuitry 210 may be formed by a common process (e.g., CMOS process), so that adding elements and functionalities, such as ECC, more typically found on a memory controller 120 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 120 may also be used to fabricate system control logic 260, row control circuitry 220, and column control circuitry 210). Thus, while moving such circuits from a die such as memory 2 die 201 may reduce the number of steps needed to fabricate such a die, adding such circuits to a die such as control die 211 may not require many additional process steps. The control die 211 could also be referred to as a CMOS die, due to the use of CMOS technology to implement some or all of control circuitry 260, 210, 220.

FIG. 2B shows column control circuitry 210 including sense amplifier(s) 230 on the control die 211 coupled to memory structure 202 on the memory die 201 through electrical paths 206. For example, electrical paths 206 may provide electrical connection between column decoder 212, driver circuitry 214, and block select 216 and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of the memory die 201, which are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical paths 206, including a pair of bond pads, which connects to column control circuitry 210. Similarly, row control circuitry 220, including row decoder 222, array drivers 224, and block select 226 are coupled to memory structure 202 through electrical paths 208. Each of electrical path 208 may correspond to a word line, dummy word line, or select gate line. Additional electrical paths may also be provided between control die 211 and memory die 201.

For purposes of this document, the phrases “a control circuit” or “one or more control circuits” can include any one of or any combination of memory controller 120, state machine 262, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, a microcontroller, a microprocessor, and/or other similar functioned circuits. The control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, FGA, ASIC, integrated circuit, or other type of circuit.

In some embodiments, there is more than one control die 211 and more than one memory die 201 in an integrated memory assembly 207. In some embodiments, the integrated memory assembly 207 includes a stack of multiple control die 211 and multiple memory die 201. FIG. 3A depicts a side view of an embodiment of an integrated memory assembly 207 stacked on a substrate 271 (e.g., a stack comprising control dies 211 and memory dies 201). The integrated memory assembly 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control die 211.

Each control die 211 is affixed (e.g., bonded) to at least one of the memory dies 201. Some of the bond pads 282/284 are depicted. There may be many more bond pads. A space between two dies 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. This solid layer 280 protects the electrical connections between the dies 201, 211, and further secures the dies together. Various materials may be used as solid layer 280, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA.

The integrated memory assembly 207 may for example be stacked with a stepped offset, leaving the bond pads at each level uncovered and accessible from above. Wire bonds 270 connected to the bond pads connect the control die 211 to the substrate 271. A number of such wire bonds may be formed across the width of each control die 211 (i.e., into the page of FIG. 3A).

A memory die through silicon via (TSV) 276 may be used to route signals through a memory die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211. The TSVs 276, 278 may be formed before, during or after formation of the integrated circuits in the semiconductor dies 201, 211. The TSVs may be formed by etching holes through the wafers. The holes may then be lined with a barrier against metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package. The solder balls 272 may form a part of the interface between integrated memory assembly 207 and memory controller 120.

FIG. 3B depicts a side view of another embodiment of an integrated memory assembly 207 stacked on a substrate 271. The integrated memory assembly 207 of FIG. 3B has three control die 211 and three memory die 201. In some embodiments, there are many more than three memory dies 201 and many more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, a control die 211 may be bonded to two or more memory die 201.

Some of the bond pads 282, 284 are depicted. There may be many more bond pads. A space between two dies 201, 211 that are bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. In contrast to the example in FIG. 3A, the integrated memory assembly 207 in FIG. 3B does not have a stepped offset. A memory die through silicon via (TSV) 276 may be used to route signals through a memory die 201. A control die through silicon via (TSV) 278 may be used to route signals through a control die 211.

Solder balls 272 may optionally be affixed to contact pads 274 on a lower surface of substrate 271. The solder balls 272 may be used to couple the integrated memory assembly 207 electrically and mechanically to a host device such as a printed circuit board. Solder balls 272 may be omitted where the integrated memory assembly 207 is to be used as an LGA package.

As has been briefly discussed above, the control die 211 and the memory die 201 may be bonded together. Bond pads on each die 201, 211 may be used to bond the two dies together. In some embodiments, the bond pads are bonded directly to each other, without solder or other added material, in a so-called Cu-to-Cu bonding process. In a Cu-to-Cu bonding process, the bond pads are controlled to be highly planar and formed in a highly controlled environment largely devoid of ambient particulates that might otherwise settle on a bond pad and prevent a close bond. Under such properly controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds may be formed at room temperature, though heat may also be applied. In embodiments using Cu-to-Cu bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 5 μm to 5 μm. While this process is referred to herein as Cu-to-Cu bonding, this term may also apply even where the bond pads are formed of materials other than Cu.

When the area of bond pads is small, it may be difficult to bond the semiconductor dies together. The size of, and pitch between, bond pads may be further reduced by providing a film layer on the surfaces of the semiconductor dies including the bond pads. The film layer is provided around the bond pads. When the dies are brought together, the bond pads may bond to each other, and the film layers on the respective dies may bond to each other. Such a bonding technique may be referred to as hybrid bonding. In embodiments using hybrid bonding, the bond pads may be about 5 μm square and spaced from each other with a pitch of 1 μm to 5 μm. Bonding techniques may be used providing bond pads with even smaller (or greater) sizes and pitches.

Some embodiments may include a film on surface of the dies 201, 211. Where no such film is initially provided, a space between the dies may be under filled with an epoxy or other resin or polymer. The under-fill material may be applied as a liquid which then hardens into a solid layer. This under-fill step protects the electrical connections between the dies 201, 211, and further secures the dies together. Various materials may be used as under-fill material, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., having offices in California, USA.

FIG. 4 is a perspective view of a portion of one example embodiment of a monolithic three dimensional memory array/structure that can comprise memory structure 202, which includes a plurality non-volatile memory cells arranged as vertical NAND strings. For example, FIG. 4 shows a portion 400 of one block of memory. The structure depicted includes a set of bit lines BL positioned above a stack 401 of alternating dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. As will be explained below, in one embodiment the alternating dielectric layers and conductive layers are divided into four or five (or a different number of) regions (also referred to as sub-blocks) by isolation regions IR. FIG. 4 shows one isolation region IR separating two sub-blocks. Below the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that in FIG. 4 , the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. Thus, the non-volatile memory cells are arranged in memory holes. More details of the three dimensional monolithic memory array that comprises memory structure 202 is provided below.

FIG. 4A is a block diagram explaining one example organization of memory structure 202, which is divided into two planes 402 and 404. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, blocks can be divided into sub-blocks and the sub-blocks can be the unit of erase. In some embodiments, sub-blocks of a block can be independently programmed without programming other sub-blocks of the block. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable the signaling and selection circuits. In some embodiments, a block represents a groups of connected memory cells as the memory cells of a block share a common set of word lines. For example, the word lines for a block are all connected to all of the vertical NAND strings for that block. Although FIG. 4A shows two planes 402/404, more or less than two planes can be implemented. In some embodiments, memory structure 202 includes eight planes.

FIGS. 4B-4G depict an example three dimensional (“3D”) NAND structure that corresponds to the structure of FIG. 4 and can be used to implement memory structure 202 of FIGS. 2A and 2B. FIG. 4B is a block diagram depicting a top view of a portion 406 of Block 2 of plane 402. As can be seen from FIG. 4B, the block depicted in FIG. 4B extends in the direction of 432. In one embodiment, the memory array has many layers; however, FIG. 4B only shows the top layer.

FIG. 4B depicts a plurality of circles that represent the memory holes, which are also referred to as vertical columns. Each of the memory holes/vertical columns include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each memory hole/vertical column implements a NAND string. For example, FIG. 4B labels a subset of the memory holes/vertical columns/NAND strings 432, 436, 446. 456, 462, 466, 472, 474 and 476.

FIG. 4B also depicts a set of bit lines 415, including bit lines 411, 412, 413, 414, . . . 419. FIG. 4B shows twenty four bit lines because only a portion of the block is depicted. It is contemplated that more than twenty four bit lines connected to memory holes/vertical columns of the block. Each of the circles representing memory holes/vertical columns has an “x” to indicate its connection to one bit line. For example, bit line 411 is connected to memory holes/vertical columns 436, 446, 456, 466 and 476.

The block depicted in FIG. 4B includes a set of isolation regions 482, 484, 486 and 488, which are formed of SiO₂; however, other dielectric materials can also be used. Isolation regions 482, 484, 486 and 488 serve to divide the top layers of the block into five regions; for example, the top layer depicted in FIG. 4B is divided into regions 430, 440, 450, 460 and 470 all of which can be referred to as sub-blocks. In one embodiment, the isolation regions only divide the layers used to implement select gates so that NAND strings in different sub-blocks can be independently selected. In one example implementation, a bit line connects to one memory hole/vertical column/NAND string in each of regions (sub-blocks) 430, 440, 450, 460 and 470. In that implementation, each block has twenty four rows of active columns and each bit line connects to five rows in each block. In one embodiment, all of the five memory holes/vertical columns/NAND strings connected to a common bit line are connected to the same set of word lines; therefore, the system uses the drain side selection lines to choose one (or another subset) of the five to be subjected to a memory operation (program, verify, read, and/or erase). In one embodiment, each of the sub-blocks of a block include a subset of the NAND strings of the block such that each of the NAND strings is positioned in only one of the sub-blocks.

FIG. 4B also shows Line Interconnects LI, which are metal connections to the source line SL from above the memory array. Line Interconnects LI are positioned adjacent regions 430 and 470.

Although FIG. 4B shows each region 430, 440, 450, 460 and 470 having four rows of memory holes/vertical columns, five regions and twenty four rows of memory holes/vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of memory holes/vertical columns per region and more or less rows of vertical columns per block. FIG. 4B also shows the memory holes/vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the memory holes/vertical columns are not staggered.

FIG. 4C depicts a portion of one embodiment of a three dimensional memory structure 202 showing a cross-sectional view along line AA of FIG. 4B. This cross sectional view cuts through memory holes/vertical columns (NAND strings) 472 and 474 of region 470 (see FIG. 4B). The structure of FIG. 4C includes three drain side select layers SGD0, SGD1 and SGD2; three source side select layers SGS0, SGS1, and SGS2; three drain side GIDL generation transistor layers SGDT0, SGDT1, and SGDT2; three source side GIDL generation transistor layers SGSB0, SGSB1, and SGSB2; four drain side dummy word line layers DD0, DD1, DD2 and DD3; four source side dummy word line layers DS0, DS1, DS2 and DS3; two hundred and forty word line layers WL0-WL239 for connecting to data memory cells, and dielectric layers DL. Other embodiments can implement more or less than the numbers described above for FIG. 4C. In one embodiment, SGD0, SGD1 and SGD2 are connected together; and SGS0, SGS1 and SGS2 are connected together. In other embodiments, more or less number of SGDs (greater or lesser than three) are connected together, and more or less number of SGSs (greater or lesser than three) connected together.

As will be discussed in more detail below, erasing the memory cells is performed using gate induced drain leakage (GIDL), which includes generating charge carriers at the GIDL generation transistors such that the carriers get injected into the charge trapping layers of the NAND strings to change threshold voltage of the memory cells. FIG. 4C shows three GIDL generation transistors at each end of the NAND string; however, in other embodiments there are more or less than three. Embodiments that use GIDL at both sides of the NAND string may have GIDL generation transistors at both sides. Embodiments that use GIDL at only the drain side of the NAND string may have GIDL generation transistors only at the drain side. Embodiments that use GIDL at only the source side of the NAND string may have GIDL generation transistors only at the source side.

FIG. 4C shows three GIDL generation transistors at each end of the NAND string. It is likely that charge carriers are only generated by GIDL at one of the three GIDL generation transistors at each end of the NAND string. Based on process variances during manufacturing, it is likely that one of the three GIDL generation transistors at an end of the NAND string is best suited for GIDL. For example, the GIDL generation transistors have an abrupt pn junction to generate the charge carriers for GIDL and, during fabrication, a phosphorous diffusion is performed at the polysilicon channel of the GIDL generation transistors. In some cases, the GIDL generation transistor with the shallowest phosphorous diffusion is the GIDL generation transistor that generates the charge carriers during erase. However, in some embodiments charge carriers can be generated by GIDL at multiple GIDL generation transistors at a particular side of the NAND string.

Memory holes/Vertical columns 472 and 474 are depicted protruding through the drain side select layers, source side select layers, dummy word line layers, GIDL generation transistor layers and word line layers. In one embodiment, each memory hole/vertical column comprises a vertical NAND string. Below the memory holes/vertical columns and the layers listed below is substrate 453, an insulating film 454 on the substrate, and source line SL. The NAND string of memory hole/vertical column 472 has a source end at a bottom of the stack and a drain end at a top of the stack. As in agreement with FIG. 4B, FIG. 4C show vertical memory hole/column 472 connected to bit line 414 via connector 417.

For ease of reference, drain side select layers; source side select layers, dummy word line layers, GIDL generation transistor layers and data word line layers collectively are referred to as the conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and Tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metal such as Tungsten, metal silicide, such as nickel silicide, tungsten silicide, aluminum silicide or the combination thereof. In some embodiments, different conductive layers can be formed from different materials. Between conductive layers are dielectric layers DL. In one embodiment, the dielectric layers are made from SiO₂. In other embodiments, other dielectric materials can be used to form the dielectric layers.

The non-volatile memory cells are formed along memory holes/vertical columns which extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. The word line layers WL0-W239 connect to memory cells (also called data memory cells). Dummy word line layers connect to dummy memory cells. A dummy memory cell does not store and is not eligible to store host data (data provided from the host, such as data from a user of the host), while a data memory cell is eligible to store host data. In some embodiments, data memory cells and dummy memory cells may have a same structure. Drain side select layers SGD0, SGD1, and SGD2 are used to electrically connect and disconnect NAND strings from bit lines. Source side select layers SGS0, SGS1, and SGS2 are used to electrically connect and disconnect NAND strings from the source line SL.

FIG. 4D depicts a portion of one embodiment of a three dimensional memory structure 202 showing a cross-sectional view along line BB of FIG. 4B. This cross sectional view cuts through memory holes/vertical columns (NAND strings) 432 and 434 of region 430 (see FIG. 4B). FIG. 4D shows the same alternating conductive and dielectric layers as FIG. 4C. FIG. 4D also shows isolation region 482. Isolation regions 482, 484, 486 and 488) occupy space that would have been used for a portion of the memory holes/vertical columns/NAND stings. For example, isolation region 482 occupies space that would have been used for a portion of memory hole/vertical column 434. More specifically, a portion (e.g., half the diameter) of vertical column 434 has been removed in layers SGDT0, SGDT1, SGDT2, SGD0, SGD1, SGD2, DD0, DD1 and DD2 to accommodate isolation region 482. Thus, while most of the vertical column 434 is cylindrical (with a circular cross section), the portion of vertical column 434 in layers SGDT0, SGDT1, SGDT2, SGD0, SGD1, SGD2, DD0, DD1 and DD2 has a semi-circular cross section. In one embodiment, after the stack of alternating conductive and dielectric layers is formed, the stack is etched to create space for the isolation region and that space is then filled in with SiO₂.

FIG. 4E depicts a cross sectional view of region 429 of FIG. 4C that includes a portion of memory hole/vertical column 472. In one embodiment, the memory holes/vertical columns are round; however, in other embodiments other shapes can be used. In one embodiment, memory hole/vertical column 472 includes an inner core layer 490 that is made of a dielectric, such as SiO₂. Other materials can also be used. Surrounding inner core 490 is polysilicon channel 491. Materials other than polysilicon can also be used. Note that it is the channel 491 that connects to the bit line and the source line. Surrounding channel 491 is a tunneling dielectric 492. In one embodiment, tunneling dielectric 492 has an ONO structure. Surrounding tunneling dielectric 492 is charge trapping layer 493, such as (for example) Silicon Nitride. Other memory materials and structures can also be used. The technology described herein is not limited to any particular material or structure.

FIG. 4E depicts dielectric layers DL as well as word line layers WL234, WL235, WL236, WL237, and WL238. Each of the word line layers includes a word line region 496 surrounded by an aluminum oxide layer 497, which is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer can be a vertical layer parallel and adjacent to charge trapping layer 493. The physical interaction of the word line layers with the vertical column forms the memory cells. Thus, a memory cell, in one embodiment, comprises channel 491, tunneling dielectric 492, charge trapping layer 493, blocking oxide layer 498, aluminum oxide layer 497 and word line region 496. For example, word line layer WL238 and a portion of memory hole/vertical column 472 comprise a memory cell MC1. Word line layer WL237 and a portion of memory hole/vertical column 472 comprise a memory cell MC2. Word line layer WL236 and a portion of memory hole/vertical column 472 comprise a memory cell MC3. Word line layer WL235 and a portion of memory hole/vertical column 472 comprise a memory cell MC4. Word line layer WL234 and a portion of memory hole/vertical column 472 comprise a memory cell MC5. In other architectures, a memory cell may have a different structure; however, the memory cell would still be the storage unit.

When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 493 which is associated with (e.g. in) the memory cell. These electrons are drawn into the charge trapping layer 493 from the channel 491, through the tunneling dielectric 492, in response to an appropriate voltage on word line region 496. The threshold voltage (Vth) of a memory cell is increased in proportion to the amount of stored charge. In one embodiment, the programming is achieved through Fowler-Nordheim tunneling of the electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasing is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

FIG. 4F is a schematic diagram of a portion of the memory structure 202 depicted in in FIGS. 4-4E. FIG. 4F shows physical data word lines WL0-WL239 running across the entire block. The structure of FIG. 4F corresponds to a portion 406 in Block 2 of FIG. 4A, including bit line 411. Within the block, in one embodiment, each bit line is connected to five NAND strings. Thus, FIG. 4F shows bit line connected to NAND string NS0 (which corresponds to memory hole/vertical column 436), NAND string NS1 (which corresponds to memory hole/vertical column 446), NAND string NS2 (which corresponds to vertical column 456), NAND string NS3 (which corresponds to memory hole/vertical column 466), and NAND string NS4 (which corresponds to memory hole/vertical column 476). As mentioned above, in one embodiment, SGD0, SGD1 and SGD2 are connected together to operate as a single logical select gate for each sub-block separated by isolation regions (482, 484, 486 and 486) to form SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4. SGS0, SGS1 and SGS2 are also connected together to operate as a single logical select gate that is represented in FIG. 4F as SGS. Although the select gates SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4 are isolated from each other due to the isolation regions, the data word lines WL0-WL239 of each sub-block are connected together. Thus, data word lines WL0-WL239 are connected to NAND strings (and memory cells) of each (or every) sub-block of a block.

The isolation regions (482, 484, 486 and 486) are used to allow for separate control of sub-blocks. A first sub-block corresponds to those vertical NAND strings controlled by SGD-s0. A second sub-block corresponds to those vertical NAND strings controlled by SGD-s1. A third sub-block corresponds to those vertical NAND strings controlled by SGD-s2. A fourth sub-block corresponds to those vertical NAND strings controlled by SGD-s3. A fifth sub-block corresponds to those vertical NAND strings controlled by SGD-s4.

FIG. 4F only shows NAND strings connected to bit line 411. However, a full schematic of the block would show every bit line and five vertical NAND strings (that are in separate sub-blocks) connected to each bit line.

Although the example memories of FIGS. 4-4F are three dimensional memory structure that includes vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein.

The memory systems discussed above can be erased, programmed and read. At the end of a successful programming process, the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. FIG. 5A is a graph of threshold voltage versus number of memory cells, and illustrates example threshold voltage distributions for the memory array when each memory cell stores one bit of data per memory cell. Memory cells that store one bit of data per memory cell data are referred to as single level cells (“SLC”). The data stored in SLC memory cells is referred to as SLC data; therefore, SLC data comprises one bit per memory cell. Data stored as one bit per memory cell is SLC data. FIG. 5A shows two threshold voltage distributions: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Memory cells that have threshold voltages in threshold voltage distribution E are, therefore, in the erased data state (e.g., they are erased). Memory cells that have threshold voltages in threshold voltage distribution P are, therefore, in the programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data “1” and programmed memory cells store data “0.” FIG. 5A depicts read reference voltage Vr. By testing (e.g., performing one or more sense operations) whether the threshold voltage of a given memory cell is above or below Vr, the system can determine a memory cells is erased (state E) or programmed (state P). FIG. 5A also depicts verify reference voltage Vv. In some embodiments, when programming memory cells to data state P, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv.

FIGS. 5B-D illustrate example threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are referred to as multi-level cells (“MLC”). The data stored in MLC memory cells is referred to as MLC data; therefore, MLC data comprises multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. In the example embodiment of FIG. 5B, each memory cell stores two bits of data. Other embodiments may use other data capacities per memory cell (e.g., such as three, four, or five bits of data per memory cell).

FIG. 5B shows a first threshold voltage distribution E for erased memory cells. Three threshold voltage distributions A, B and C for programmed memory cells are also depicted. In one embodiment, the threshold voltages in the distribution E are negative and the threshold voltages in distributions A, B and C are positive. Each distinct threshold voltage distribution of FIG. 5B corresponds to predetermined values for the set of data bits. In one embodiment, each bit of data of the two bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP) and an upper page (UP). In other embodiments, all bits of data stored in a memory cell are in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. Table 1 provides an example encoding scheme.

TABLE 1 E A B C LP 1 0 0 1 UP 1 1 0 0

In one embodiment, known as full sequence programming, memory cells can be programmed from the erased data state E directly to any of the programmed data states A, B or C using the process of FIG. 6 (discussed below). For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state E. Then, a programming process is used to program memory cells directly into data states A, B, and/or C. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and/or from data state E to data state C. The arrows of FIG. 5B represent the full sequence programming. In some embodiments, data states A-C can overlap, with memory controller 120 (or control die 211) relying on error correction to identify the correct data being stored.

FIG. 5C depicts example threshold voltage distributions for memory cells where each memory cell stores three bits of data per memory cells (which is another example of MLC data). FIG. 5C shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) Er represents memory cells that are erased. The other seven threshold voltage distributions (data states) A-G represent memory cells that are programmed and, therefore, are also called programmed states. Each threshold voltage distribution (data state) corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. In one embodiment, data values are assigned to the threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory erroneously shifts to its neighboring physical state, only one bit will be affected. Table 2 provides an example of an encoding scheme for embodiments in which each bit of data of the three bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP), middle page (MP) and an upper page (UP).

TABLE 2 Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

FIG. 5C shows seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from memory cells. By testing (e.g., performing sense operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine what data state (i.e., A, B, C, D, . . . ) a memory cell is in.

FIG. 5C also shows seven verify reference voltages, VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming memory cells to data state A, the system will test whether those memory cells have a threshold voltage greater than or equal to VvA. When programming memory cells to data state B, the system will test whether the memory cells have threshold voltages greater than or equal to VvB. When programming memory cells to data state C, the system will determine whether memory cells have their threshold voltage greater than or equal to VvC. When programming memory cells to data state D, the system will test whether those memory cells have a threshold voltage greater than or equal to VvD. When programming memory cells to data state E, the system will test whether those memory cells have a threshold voltage greater than or equal to VvE. When programming memory cells to data state F, the system will test whether those memory cells have a threshold voltage greater than or equal to VvF. When programming memory cells to data state G, the system will test whether those memory cells have a threshold voltage greater than or equal to VvG. FIG. 5C also shows Vev, which is a voltage level to test whether a memory cell has been properly erased.

In an embodiment that utilizes full sequence programming, memory cells can be programmed from the erased data state Er directly to any of the programmed data states A-G using the process of FIG. 6 (discussed below). For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state Er. Then, a programming process is used to program memory cells directly into data states A, B, C, D, E, F, and/or G. For example, while some memory cells are being programmed from data state Er to data state A, other memory cells are being programmed from data state Er to data state B and/or from data state Er to data state C, and so on. The arrows of FIG. 5C represent the full sequence programming. In some embodiments, data states A-G can overlap, with control die 211 and/or memory controller 120 relying on error correction to identify the correct data being stored. Note that in some embodiments, rather than using full sequence programming, the system can use multi-pass programming processes known in the art.

In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation (e.g., see read compare levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG, of FIG. 5C) or verify operation (e.g. see verify target levels VvA, VvB, VvC, VvD, VvE, VvF, and VvG of FIG. 5C) in order to determine whether a threshold voltage of the concerned memory cell has reached such level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, then it is assumed that the memory cell did not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, the unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased).

There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate it discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or fails to allow) the NAND string that includes the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see whether it has been discharged or not. Note that the technology described herein can be used with different methods known in the art for verifying/reading. Other read and verify techniques known in the art can also be used.

FIG. 5D depicts threshold voltage distributions when each memory cell stores four bits of data, which is another example of MLC data. FIG. 5D depicts that there may be some overlap between the threshold voltage distributions (data states) S0-S15. The overlap may occur due to factors such as memory cells losing charge (and hence dropping in threshold voltage). Program disturb can unintentionally increase the threshold voltage of a memory cell. Likewise, read disturb can unintentionally increase the threshold voltage of a memory cell. Over time, the locations of the threshold voltage distributions may change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read reference voltages can help to mitigate such effects. Using ECC during the read process can fix errors and ambiguities. Note that in some embodiments, the threshold voltage distributions for a population of memory cells storing four bits of data per memory cell do not overlap and are separated from each other. The threshold voltage distributions of FIG. 5D will include read reference voltages and verify reference voltages, as discussed above.

When using four bits per memory cell, the memory can be programmed using the full sequence programming discussed above, or multi-pass programming processes known in the art. Each threshold voltage distribution (data state) of FIG. 5D corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. Table 3 provides an example of an encoding scheme for embodiments in which each bit of data of the four bits of data stored in a memory cell are in different logical pages, referred to as a lower page (LP), middle page (MP), an upper page (UP) and top page (TP).

TABLE 3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 TP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 UP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 FIG. 6 is a flowchart describing one embodiment of a process for programming memory cells. For purposes of this document, the term program and programming are synonymous with write and writing. In one example embodiment, the process of FIG. 6 is performed for memory structure 202 using the one or more control circuits (e.g., system control logic 260, column control circuitry 210, row control circuitry 220) discussed above. In one example embodiment, the process of FIG. 6 is performed by integrated memory assembly 207 using the one or more control circuits (e.g., system control logic 260, column control circuitry 210, row control circuitry 220) of control die 211 to program memory cells on memory die 201. The process includes multiple loops, each of which includes a program phase and a verify phase. The process of FIG. 6 is performed to implement the full sequence programming, as well as other programming schemes including multi-stage programming. When implementing multi-stage programming, the process of FIG. 6 is used to implement any/each stage of the multi-stage programming process.

Typically, the program voltage applied to the control gates (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 602 of FIG. 6 , the programming voltage signal (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level) and a program counter PC maintained by state machine 262 is initialized at 1. In one embodiment, the group of memory cells selected to be programmed (referred to herein as the selected memory cells) are programmed concurrently and are all connected to the same word line (the selected word line). There will likely be other memory cells that are not selected for programming (unselected memory cells) that are also connected to the selected word line. That is, the selected word line will also be connected to memory cells that are supposed to be inhibited from programming. Additionally, as memory cells reach their intended target data state, they will be inhibited from further programming. Those NAND strings (e.g., unselected NAND strings) that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. When a channel has a boosted voltage, the voltage differential between the channel and the word line is not large enough to cause programming. To assist in the boosting, in step 604 the control die will pre-charge channels of NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming. In step 606, NAND strings that include memory cells connected to the selected word line that are to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as “unselected NAND strings.” In one embodiment, the unselected word lines receive one or more boosting voltages (e.g., ˜7-11 volts) to perform boosting schemes. A program inhibit voltage is applied to the bit lines coupled the unselected NAND string.

In step 608, a program voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell on a NAND string should be programmed, then the corresponding bit line is biased at a program enable voltage. In step 608, the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently (unless they are inhibited from programming). That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this manner all of the memory cells connected to the selected word line will concurrently have their threshold voltage change, unless they are inhibited from programming.

In step 610, program verify is performed and memory cells that have reached their target states are locked out from further programming by the control die. Step 610 includes performing verification of programming by sensing at one or more verify reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage. In step 610, a memory cell may be locked out after the memory cell has been verified (by a test of the Vt) that the memory cell has reached its target state.

If, in step 612, it is determined that all of the memory cells have reached their target threshold voltages (pass), the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 614. Otherwise if, in step 612, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 616.

In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distribution are counted. That is, the number of memory cells that have, so far, failed to reach their target state are counted. This counting can be done by state machine 262, memory controller 120, or another circuit. In one embodiment, there is one total count, which reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, separate counts are kept for each data state.

In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, then the programming process can stop and a status of “PASS” is reported in step 614. In this situation, enough memory cells programmed correctly such that the few remaining memory cells that have not been completely programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 618 is below the number of bits that can be corrected by error correction codes (ECC) during a read process to allow for future/additional errors. When programming less than all of the memory cells for a page, or comparing a count for only one data state (or less than all states), then the predetermined limit can be a portion (pro-rata or not pro-rata) of the number of bits that can be corrected by ECC during a read process for the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria.

If the number of failed memory cells is not less than the predetermined limit, then the programming process continues at step 620 and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 6, 12, 16, 19, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step 624. If the program counter PC is less than the program limit value PL, then the process continues at step 626 during which time the Program Counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped up to the next magnitude. For example, the next pulse will have a magnitude greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1-1.0 volts). After step 626, the process loops back to step 604 and another program pulse is applied to the selected word line (by the control die) so that another iteration (steps 604-626) of the programming process of FIG. 6 is performed.

In one embodiment memory cells are erased prior to programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from state P to state E of FIG. 5A, from states A/B/C to state E of FIG. 5B, from states A-G to state Er of FIG. 5C or from states S1-S15 to state S0 of FIG. 5D.

One technique to erase memory cells in some memory devices is to bias a p-well (or other types of) substrate to a high voltage to charge up a NAND channel. An erase enable voltage (e.g., a low voltage) is applied to control gates of memory cells while the NAND channel is at a high voltage to erase the memory cells. Herein, this is referred to as p-well erase.

Another approach to erasing memory cells is to generate gate induced drain leakage (“GIDL”) current to charge up the NAND string channel. An erase enable voltage is applied to control gates of the memory cells, while maintaining the NAND string channel potential to erase the memory cells. Herein, this is referred to as GIDL erase. Both p-well erase and GIDL erase may be used to lower the threshold voltage (Vt) of memory cells.

In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a GIDL generation transistor (e.g., transistors connected to SGDT0, SGDT1, SGDT2, SGSB0, SGSB1 and SGSB2). In some embodiments, a select gate (e.g., SGD or SGS) can be used as a GIDL generation transistor. A transistor drain-to-gate voltage that generates a GIDL current is referred to herein as a GIDL voltage. The GIDL current may result when the GIDL generation transistor drain voltage is significantly higher than the GIDL generation transistor control gate voltage. GIDL current is a result of carrier generation, i.e., electron-hole pair generation due to band-to-band tunneling and/or trap-assisted generation. In one embodiment, GIDL current may result in one type of carriers (also referred to a charge carriers), e.g., holes, predominantly moving into the NAND channel, thereby raising or changing the potential of the channel. The other type of carriers, e.g., electrons, are extracted from the channel, in the direction of a bit line or in the direction of a source line, by an electric field. During erase, the holes may tunnel from the channel to a charge storage region of the memory cells (e.g., to charge trapping layer 493) and recombine with electrons there, to lower the threshold voltage of the memory cells.

The GIDL current may be generated at either end (or both ends) of the NAND string. A first GIDL voltage may be created between two terminals of a GIDL generation transistor (e.g., connected to SGDT0, SGDT1, SGDT2) that is connected to or near a bit line to generate a first GIDL current. A second GIDL voltage may be created between two terminals of a GIDL generation transistor (e.g., SGSB0, SGSB1 and SGSB2) that is connected to or near a source line to generate a second GIDL current. Erasing based on GIDL current at only one end of the NAND string is referred to as a one-sided GIDL erase. Erasing based on GIDL current at both ends of the NAND string is referred to as a two-sided GIDL erase. The technology described herein can be used with one-sided GIDL erase and two-sided GIDL erase.

FIG. 7 depicts the movement of holes and electrons in a NAND string 800 during a two-sided GIDL erase. An example NAND string 800 is depicted that includes a channel 891 connected to a bit line (BL) and to a source line (SL). A tunnel dielectric layer (TNL) 892, charge trapping layer (CTL) 893, and a blocking oxide layer (BOX) 898 are layers which extend around the memory hole of the NAND string (see discussion above). Different regions of the channel layers represent channel regions which are associated with respective memory cells or select gate transistors.

Solely for purposes of simplifying the drawing and the discussion, only one drain side GIDL generation transistor 801 (e.g., representing one of SGDT0, SGDT1 or SGDT2) is depicted in FIG. 7 and only one source side GIDL generation transistor 802 (e.g., representing one of SGSB0, SGSB1 or SGSB2) is depicted in FIG. 7 . Also, solely for purposes of simplifying the discussion, the select gates (i.e. SGS and SGD) of NAND string 800 are not depicted in FIG. 7 . However, FIG. 7 does show NAND string 800 including memory cells 810, 815, 820, and 825; control gates 811, 816, 821, and 826; CTL regions 813, 818, 823, and 828; and channel regions 812, 817, 822, and 827, respectively. NAND string 800 also includes memory cells 860, 865, 870, and 875; control gates 861, 866, 871, and 876; CTL regions 863, 868, 873, and 878; and channel regions 862, 867, 872, and 877, respectively.

During an erase operation, an erase voltage Vera (e.g., ˜20V) is applied to both the bit line (BL) and to the source line (SL). A voltage V GIDL (e.g., Vera-5V) is applied to the gate 806 of the GIDL generation transistor 801 and to the gate 856 of GIDL generation transistor 802 to enable GIDL. Representative holes are depicted in the channel layers as circles with a “+” sign and representative electrons are depicted in the channel layers as circles with a “−” sign. Electron-hole pairs are generated by a GIDL process. Initially, during an erase operation, the electron-hole pairs are generated at the GIDL generation transistors. The holes move away from the driven ends into the channel, thereby charging the channel to a positive potential. The electrons generated at the GIDL generation transistor 801 move toward the bit line (BL) due to the positive potential there. The electrons generated at the GIDL generation transistor 802 move toward the source line (SL) due to the positive potential there. Subsequently, during the erase period of each memory cell, additional holes are generated by GIDL at virtual junctions which are formed in the channel at the edges of the control gate of the memory cells. Some holes are removed from the channel as they tunnel to the CTL regions.

Electrons are also generated by the GIDL process. Initially, during the erase operation, the electrons are generated at the GIDL generation transistors and move toward the driven ends. Subsequently, during the erase period of each storage element, additional electrons are generated by GIDL at virtual junctions, which are formed in the channel at the edges of the control gate of the memory cells.

At one end (e.g., drain side) of the NAND string, example electrons 840 and 841 move toward the bit line. Electron 840 is generated at the GIDL generation transistor 801 and electron 841 is generated at a junction of the memory cell 815 in the channel region 817. Also, in the drain side, example holes including a hole 842 moving away from the bit line as indicated by arrows. The hole 842 is generated at a junction of memory cell 815 in the channel region 817 and can tunnel into the CTL region 818 as indicated by arrow 843.

At the other end (e.g., source side) of the NAND string, example electrons 845 and 849 move toward the source line. Electron 845 is generated at the GIDL generation transistor 802 and electron 849 is generated at a junction of the memory cell 865 in the channel region 867. Also, at the source side, example holes including a hole 847 move away from the source line and hole 847 is generated at a junction of the memory 865 in the channel region 867 and can tunnel into the CTL region 868 as indicated by arrow 848.

FIG. 8 is a flow chart describing one embodiment of a traditional process for erasing non-volatile memory. In one example implementation, the process of FIG. 8 utilizes the two sided GIDL erase described by FIG. 7 . In another embodiment, the process of FIG. 8 utilizes the one sided GIDL erase (GIDL at either the source side only or the drain side only). The process of FIG. 8 can be performed by any one of the one or more control circuits discussed above. For example, the process of FIG. 8 can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In one example, the process of FIG. 8 is performed by or at the direction of state machine 262, using other components of System Control Logic 260, Column Control Circuitry 210 And Row Control Circuitry 220. In another embodiment, the process of FIG. 8 is performed by or at the direction of memory controller 120. In one embodiment, the process of erasing is performed on a block of memory cells. That is, in one embodiment a block is the unit of erase.

In step 902 of FIG. 8 , the magnitude of the initial erase voltage pulse (Vera) is set. One example of an initial magnitude is 20 volts. However, other initial magnitudes can also be used. In step 904, an erase voltage pulse is applied to the NAND strings of the block. In one embodiment of two sided GIDL erase, the erase voltage pulse is applied to the bit lines and the source line. In one embodiment of one sided GIDL erase, the erase voltage pulse is applied to the source line. In another embodiment of one sided GIDL erase, the erase voltage pulse is applied to the bit lines.

In step 906, erase verify is performed separately for each sub-block of the block being erased. For example, in an embodiment with five sub-blocks (e.g., sub-blocks 430, 440, 450, 460 and 470 of FIG. 4B), first step 906 is performed for sub-block 430, subsequently step 906 is performed for sub-block 440, subsequently step 906 is performed for sub-block 450, subsequently step 906 is performed for sub-block 460, and finally step 906 is performed for sub-block 470. In one embodiment, when performing erase verify for a sub-block, erase verify for memory cells connected to even word lines is performed separately from performing erase verify for memory cells connected to odd word lines. That is, the control circuit will perform erase verify for those memory cells connected to even word lines while not performing erase verify for memory cells connected to odd word lines. Subsequently, the control circuit will perform erase verify for those memory cells connected to odd word lines while not performing erase verify for memory cells connected to even word lines. When performing erase verify for memory cells connected to even word lines, the even word lines will receive VCG_Vfy and odd word lines will receive Vread. The control circuit will sense the NAND strings (e.g., using the sense amplifiers) to determine if sufficient current is flowing in order to verify whether all of the memory cells of the NAND string have a threshold voltage lower than an erase verify voltage (e.g., Vev of FIG. 5C). When performing erase verify for memory cells connected to odd word lines, the odd word lines will receive VCG_Vfy and even word lines will receive Vread. The control circuit will sense the NAND strings to determine if sufficient current is flowing in order to verify whether all of the memory cells of the NAND string have a threshold voltage lower than an erase verify voltage. Those NAND strings that successfully verify erase are marked in step 908 so that they will be locked out from further erasing. In one embodiment that uses one sided GIDL erase from the source side, NAND strings can be locked out from further erasing by asserting an appropriate bit line voltage (e.g., 3.5 volts or Vread, which is ˜6 volts). In some embodiments that use two sided GIDL erase or one sided GIDL erase from the source side, NAND strings are not locked out from further erasing and step 908 is skipped.

In step 910, the control circuit determines the status of the erase verify (from step 906). If all of the NAND strings passed erase verify for odd word lines and erase verify for even word lines, then the process will continue at step 912 and return a status of “Pass” as the erase process is not completed. In some embodiments, if the number of NAND strings that have failed erase verify is less than a first threshold then the control circuit will consider the verification process to have passed and the process will also continue at step 912. If the number of NAND strings that have failed erase verify is greater than the first threshold, then the process will continue with step 914. In one embodiment, the first threshold is a number that is smaller than the number of bits that can be corrected by ECC during a read process.

In step 914, the control circuit determines whether the number of erase voltage pulses is less than or equal to a maximum number of pulses. In one example, the maximum number is six pulses. In another example, the maximum number is 20 pulses. Other examples of maximum numbers can also be used. If the number of pulses is less than or equal to the maximum number, then the control circuit will perform another loop of the erase process (e.g., steps 904-918), which includes applying another erase voltage pulse. Thus, the process will continue at step 918 to increase the magnitude of the next erase voltage pulse (e.g., by a step size between 0.1-0.25 volts) and then the process will loop back to step 904 to apply the next erase voltage pulse. If, in step 914, it is determined that the number of erase voltage pulses already applied in the current erase process is greater than the maximum number, then the erase process failed (step 916) and the current block being erased is retired from any further use by the memory system.

As discussed above, the erase verify operation comprises performing erase verify ten times, including performing erase verify for odd word lines and separately performing erase verify for even word lines for five sub-bocks. Performing erase verify ten times slows down the erase process.

Due to process differences (e.g., variations in the blocking oxide) the speed of erasing may vary among different sub-blocks. The time needed to perform the erase process may be reduced by optimization of the sequence of verifying the sub-blocks. In the past, the sub-bocks are verified in order based on location from one side of the block to the other. For example, sub-block 430 is verified first, sub-block 440 is verified second, sub-block 450 is verified third, sub-block 460 is verified fourth and sub-block 470 is verified fifth. For ease of reference, sub-block 430 can be referred to as SB0, sub-block 440 can be referred to as SB1, sub-block 450 can be referred to as SB2, sub-block 460 can be referred to as SB3, and sub-block 470 can be referred to as SB4. To optimize the sequence of verifying sub-blocks in order to reduce the time needed for the erase process, it is proposed to erase verify the sub-blocks in an order from slowest erasing sub-block to fastest erasing sub-block. The slowest erasing sub-blocks are likely to have more errors at any given time. If the number of errors in a sub-blocks exceeds the allowed number of errors, then the erases verify process can be stopped (without finishing) and the process can move on to the next erase loop.

FIG. 9 is a flow chart describing one embodiment of a process for erasing non-volatile memory. In one example implementation, the process of FIG. 9 utilizes the two sided GIDL erase described by FIG. 7 . In another embodiment, the process of FIG. 9 utilizes the one sided GIDL erase. The process of FIG. 9 can be performed by any one of the one or more control circuits discussed above. For example, the process of FIG. 9 can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In one example, the process of FIG. 9 is performed by or at the direction of state machine 262, using other components of System Control Logic 260, Column Control Circuitry 210 and Row Control Circuitry 220. In another embodiment, the process of FIG. 9 is performed by or at the direction of memory controller 120. In one embodiment, the process of erasing is performed on a block of non-volatile memory cells. That is, in one embodiment a block is the unit of erase. In another embodiment, a different grouping of memory cells can be the unit of erase.

In step 960 of FIG. 9 , relative erase speed of each portion of a group of non-volatile memory cells is determined. For example, the relative erase speed of each sub-block of a block is determined. This determination can be made for each block or a representative subset of blocks. This determination can be made for every memory die or a representative subset of memory dies. The determination of step 960 can be made at the time of manufacturing, testing or device trim. The determination can be made from experimentation on actual devices or simulation. When performing an experiment on an actual device, a series of erase pulses can be applied to the memory and then sensing operations can be used to see which sub-blocks are deeper or shallower erased. The determination of step 960 can be performed by test equipment or the control circuit. In step 962, the order of erase verify is set from slowest erasing portion of the block to fastest erasing portion of the block based on the determination of step 960.

In step 964, the control circuit sets a parameter that indicates the order from slowest erasing portion of the block to fastest erasing portion of the block. In one embodiment, the control circuit is configured to store a parameter that indicates an order of erase speed from slowest erasing portion of the group to fastest erasing portion of the group. FIG. 10 is a table indicating various values for that parameter. Seven bits (b6-b0) are used to configure the parameters to select one of 120 possible orders of the five sub-blocks (SB0-SB4). For example, setting b6-b0=“0000011” selects the order of SB4 (slowest)→SB0 (second slowest)→SB3 (third slowest)→SB2 (second fastest)→SB1 (fastest).

In step 966, the control circuit applies doses of erasing to the group of non-volatile memory cells. For example, the control circuit can apply voltage pulses at Vera to the bit lines and source lines, as explained previously with respect to step 904 and FIG. 7 .

In step 968, the control circuit performs erase verify between pairs of successive doses of erasing (see e.g., step 906). In one embodiment, the erase-verify of step 968 includes performing steps 980 and 982. In step 980, the control circuit separately performs erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group. That is, the control circuit performs erase verify for the portions of the group in the order specified by the parameter that was set in step 964. For example, if the parameter was set to b6-b0=“0000011” then the control circuit will first perform erase verify for sub-block SB4, followed by performing erase verify for sub-block SB0, followed by performing erase verify for sub-block SB3, followed by performing erase verify for sub-block SB2, and followed by performing erase verify for sub-block SB1. In one set of embodiments, erase verify is performed for even word lines (e.g., WL0, WL2, WL4, WL238) separately from performing erase verify for odd word lines (e.g., WL1, WL3, WL5, WL239); therefore, if the parameter was set to b6-b0=“0000011” then the control circuit will first perform erase verify for even word lines of sub-block SB4, followed by performing erase verify for odd word lines of sub-block SB4, followed by performing erase verify for even word lines of sub-block SB0, followed by performing erase verify for odd word lines of sub-block SB0, followed by performing erase verify for even word lines of sub-block SB3, followed by performing erase verify for odd word lines of sub-block SB3, followed by performing erase verify for even word lines of sub-block SB2, followed by performing erase verify for odd word lines of sub-block SB2, followed by performing erase verify for even word lines of sub-block SB1, and followed by performing erase verify for odd word lines of sub-block SB1.

In step 982, the control circuit aborts the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors exceeding a limit. For example, if the control circuit was performing erase verify in the order of the above-described example (SB4→SB0→SB3→SB2→SB1) and the number of erase errors exceeds the limit during erase verify for SB4, then erase verify is not performed for SB0, SB3, SB2 and SB1. In that same example, if the number of erase errors exceeds the limit during erase verify for SB3, then erase verify is not performed for SB2 and SB1. The erase errors can be the number of NAND strings that failed erase verify (e.g., threshold voltages greater than Vev—see FIG. 5C), the number of memory cells that failed erase verify, the number of even word lines that failed erase verify or the number of odd word lines that failed erase verify. By aborting the erase verify process prior to completion of erase verify for all of the portions of the group, the time spent on erase verify is shortened (which shortens the erase process). By performing erase verify in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group, it is more likely that the limit will be met earlier in the erase verify process, thereby saving more time, as the slowest erasing portion of the group is likely to have the most errors (e.g., NAND strings failing erase verify).

In one example implementation, the limit is a maximum number of erase errors per portion of the group (e.g., per sub-block) and the control circuit is configured to abort the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors for a portion of the group being erase verified exceeding the limit.

In one example implementation, the limit is a maximum number of erase errors for the group of non-volatile memory cells and the control circuit is configured to abort the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors for a portion of the group being erase verified exceeding the limit.

In one example implementation, the limit is a maximum number of erase errors for the group of non-volatile memory cells and the control circuit is configured to abort the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a cumulative number of erase errors for all portions of the group already erase verified exceeding the limit.

In one example implementation, the non-volatile memory cells are arranged in NAND strings; each portion of the group includes a different subset of the NAND strings; the group of non-volatile memory cells are connected to even word lines and odd word lines; the limit is a maximum number of erase errors per portion of the group; the control circuit is configured to perform erase verify for a portion of a group by performing erase verify for even word lines separately from performing erase verify for odd word lines; and the control circuit is configured to abort the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to either of the even word lines for a portion of the group or the odd word lines for a portion of the group having more errors than the limit.

In one example implementation, the non-volatile memory cells are arranged in NAND strings; the NAND strings are connected to even word lines and odd word lines; each portion of the group includes a different subset of the NAND strings; the limit is a maximum number of erase errors per portion of the group; the control circuit is configured to perform erase verify for a portion of a group by performing erase verify for even word lines separately from performing erase verify for odd word lines; and the control circuit is configured to abort the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a sum of errors of the even word lines and the odd word lines of the group exceeding the limit.

FIG. 11 is a flow chart describing one embodiment of a process for erasing non-volatile memory. In one embodiment, the process of FIG. 11 is an example implementation of the process of steps 966-982 of FIG. 9 . In one example implementation, the process of FIG. 11 utilizes the two sided GIDL erase described by FIG. 7 . In another embodiment, the process of FIG. 11 utilizes the one sided GIDL erase. The process of FIG. 11 can be performed by any one of the one or more control circuits discussed above. For example, the process of FIG. 11 can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In one example, the process of FIG. 11 is performed by or at the direction of state machine 262, using other components of System Control Logic 260, Column Control Circuitry 210 and Row Control Circuitry 220. In another embodiment, the process of FIG. 11 is performed by or at the direction of memory controller 120. In one embodiment, the process of erasing is performed on a block of memory cells.

In step 902 the control circuit sets the magnitude of the initial erase voltage pulse and in step 904 the erase voltage pulse is applied to the block, as discussed above with respect to FIG. 8 . Steps 908-918 of FIG. 11 are also the same as in FIG. 8 . The process of FIG. 11 differs from the process of FIG. 8 by how erase verify is performed in steps 1102-1112 of FIG. 11 .

In step 1102, the control circuit chooses the next sub-block in the sequence from slowest to fastest. For example, the control circuit accesses the parameter of FIG. 10 to determine the configured sequence of previously determined slowest erasing sub-block to previously determined fastest erasing sub-block. When erase-verify for this current erase loop starts none of the sub-blocks have been erase verified in this erase loop so the control circuit chooses the slowest to erase sub-block (the first sub-block of the sequence). The next time step 1102 is performed in the current erase loop (e.g., the erase loop is steps 904-918), the second slowest sub-block is chosen. In step 1104, erase verify is performed for even word lines of the NAND strings of the chosen sub-block. In step 1106, erase verify is performed for odd word lines of the NAND strings of the chosen sub-block.

In step 1108, it is determined whether the number of erase errors is less than the limit. In one example implementation, the limit is a maximum number of erase errors per sub-block; therefore, step 1108 includes determining whether the total number of errors detected in steps 1104 and 1108 for the current sub-block is less than the limit. In another example implementation, the limit is a maximum number of erase errors for the entire block, and step 1108 includes determining whether the total number of errors detected in steps 1104 and 1108 for the current sub-block is less than the limit. In another example implementation, the limit is a maximum number of erase errors for the entire block, and step 1108 includes determining whether the total number of errors detected in steps 1104 and 1108 for the current sub-block plus the number of errors detected for all other sub-blocks already erase verified in the current erase loop is less than the limit. If the number of errors is not less than the limit, then in step 1110 the control circuit aborts the erase verify process (e.g., aborts the current loop of steps 1102-1112) and moves on to the next erase voltage pulse by continuing at step 914.

If the number of errors is less than the limit, then in step 1112 the control circuit determines whether there are more sub-blocks that need to be erase verified. If so, the process continues at step 1102 to choose the next sub-block in the sequence and program verify that next chosen sub-block. If, in step 1112, it is determined that all sub-blocks have been erase-verified, then the process continues at step 910 to confirm the verify status (as discussed above).

FIG. 12 is a flow chart describing one embodiment of a process for erasing non-volatile memory. In one embodiment, the process of FIG. 12 is an example implementation of the process of steps 966-982 of FIG. 9 . In one example implementation, the process of FIG. 12 utilizes the two-sided GIDL erase described by FIG. 7 . In another embodiment, the process of FIG. 12 utilizes the one sided GIDL erase. The process of FIG. 12 can be performed by any one of the one or more control circuits discussed above. For example, the process of FIG. 12 can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In one example, the process of FIG. 12 is performed by or at the direction of state machine 262, using other components of System Control Logic 260, Column Control Circuitry 210 and Row Control Circuitry 220. In another embodiment, the process of FIG. 12 is performed by or at the direction of memory controller 120. In one embodiment, the process of erasing is performed on a block of memory cells.

In step 902 the control circuit sets the magnitude of the initial erase voltage pulse and in step 904 the erase voltage pulse is applied to the block, as discussed above with respect to FIG. 8 . Steps 908-918 of FIG. 12 are also the same as in FIG. 8 . The process of FIG. 12 differs from the process of FIG. 8 by how erase verify is performed in steps 1202-1214 of FIG. 12 .

In step 1202, the control circuit chooses the next sub-block in the sequence from slowest to fastest. For example, the control circuit accesses the parameter of FIG. 10 to determine the configured sequence of previously determined slowest erasing sub-block to previously determined fastest erasing sub-block. When erase-verify for this current erase loop starts none of the sub-blocks have been erase verified in this erase loop so the control circuit chooses the slowest to erase sub-block (the first sub-block in the sequence). The next time step 1202 is performed in the current erase loop (e.g., the erase loop is steps 904-918), the second slowest sub-block is chosen.

In step 1204, erase verify is performed for even word lines of the NAND strings of the chosen sub-block. In step 1206, it is determined whether the number of erase errors is less than the limit. In one example implementation, the limit is a maximum number of erase errors per sub-block; therefore, step 1206 includes determining whether the number of errors in even word lines detected in step 1204 for the current sub-block is less than the limit. In another example implementation, the limit is a maximum number of erase errors for the entire block, and step 1206 includes determining whether the number of errors in the even word lines of detected in step 1204 for the current sub-block is less than that limit. In another example implementation, the limit is a maximum number of erase errors for the entire block, and step 1206 includes determining whether the number of errors in the even word lines detected in step 1204 for the current sub-block plus the number of errors detected for all other sub-blocks erase verified in the current erase loop is less than the limit. If the number of errors is not less than the limit, then in step 1208 the control circuit aborts the erase verify process (e.g., aborts the loop of steps 1202-1214) and moves on to the next erase voltage pulse by continuing at step 914.

If the number of errors detected in step 1206 is less than the limit, then in step 1210 erase verify is performed for the odd word lines of the NAND strings of the chosen sub-block. In step 1212, it is determined whether the number of erase errors is less than the limit. In one example implementation, the limit is a maximum number of erase errors per sub-block; therefore, step 1212 includes determining whether the number of errors in the odd word lines detected in step 1210 for the current sub-block is less than the limit or whether the total number of errors in odd and even word lines for the current sub-block is less than the limit. In another example implementation, the limit is a maximum number of erase errors for the entire block, and step 1212 includes determining whether the total number of errors in even word lines and odd word lines for the current sub-block is less than the limit. In another example implementation, the limit is a maximum number of erase errors for the entire block, and step 1212 includes determining whether the total number of errors in even and odd word lines detected for the current sub-block plus the number of errors detected for all other sub-blocks erase verified in the current erase loop is less than the limit. If the number of errors is not less than the limit, then in step 1208 the control circuit aborts the erase verify process (e.g., aborts the loop of steps 1202-1214) and moves on to the next erase voltage pulse by continuing at step 914.

If the number of errors is less than the limit, then in step 1214 the control circuit determines whether there are more sub-blocks that need to be erase verified. If so, the process continues at step 1202 to choose the next sub-block in the sequence and program verify that next chosen sub-block. If, in step 1214, it is determined that all sub-blocks have been erase-verified, then the process continues at step 910 to confirm the verify status (as discussed above).

Both of FIGS. 11 and 12 are examples of performing an erase-verify portion of a particular erase loop of an erase operation for a block of non-volatile memory cells that comprises multiple erase loops including separately performing erase verify for multiple portions of the block in order from slower erasing portion of the block to faster erasing portion of the block, and aborting the performing of the erase-verify portion of the particular erase loop of the erase operation prior to completion of erase verify for all of the portions of the block and commencing the next erase loop of the erase operation in response to a number erase errors exceeding a limit.

Due to process differences (e.g., variations in the blocking oxide) the speed of programming may vary among different sub-blocks. Therefore, the time needed to perform the programming process may be reduced by optimization of the sequence of programming the sub-blocks. For example, slower programming sub-blocks are more likely to fail the programming process. That is, the programming process will be performed more efficiently (e.g., complete quicker) and with a lower chance of a disturb, if the slower programming sub-blocks are performed earlier in the process so that programming for a defective block will be stopped earlier in time. This concept can be extended to other types of memory operations, meaning that a memory operation will be more efficient if the memory operation is performed on sub-blocks in an optimized order (e.g., start with the slowest sub-blocks and/or the sub-blocks most likely to fail) so that any failure will be realized earlier and a bad process destined to fail will be stopped sooner (thereby saving time and reducing the chance of a disturb).

FIG. 13 is a flow chart describing one embodiment of a process for performing a memory operation (e.g., programming, erasing or other). Step 1302 includes determining the speed of performing a memory operation (e.g., programming, erasing or other) for the multiple portions of a group of non-volatile memory cells relative to each other. For example, step 1302 may include determining the speed of programming for multiple sub-blocks (e.g., sub-blocks 430, 440, 450, 460 and 470) of a block of non-volatile memory cells relative to each other. Step 1302 can be performed during manufacturing and test (e.g., during die sort) by test equipment or in the field by the control circuit. In another embodiment, step 1302 may include determining a ranking of sub-blocks from most likely to fail to least likely to fail.

Step 1304 includes separately performing a memory operation for multiple portions of the first group in order from a previously determined slower portion of the first group to a previously determined faster portions of the first group. For example, step 1304 may include the control circuit programming the sub-blocks of a block from a slower (or slowest) programming sub-block to a faster (or fastest) programming sub-block. In one embodiment, outer sub-blocks (e.g., sub-blocks 430 and 470 of FIG. 4B) program slower than inner sub-sub-blocks (e.g., sub-blocks 440, 450 and 460 of FIG. 4B), especially at low temperatures; therefore, step 1304 includes programming the outer sub-blocks before programming the inner sub-blocks. In another embodiment, step 1304 may include performing a memory operation for multiple portions of the first group in order from most likely to fail to least likely to fail.

With respect to step 1304, the term “separately performing” indicates the each sub-block is operated on separately. For example, each sub-block is programmed separately in a sequence as defined by step 1302.

Step 1304 can be performed by any one of the one or more control circuits discussed above. For example, the process of step 1304 can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In one example, the process of step 1304 is performed by or at the direction of state machine 262, using components of System Control Logic 260, Column Control Circuitry 210 and Row Control Circuitry 220. In another embodiment, the process of step 1304 is performed by or at the direction of memory controller 120.

The process of FIG. 6 can be used to concurrently program data into memory cells in multiple planes. For example, if a memory system (one or more die) has 4 (or more) planes, then one block from each plane can be selected for programming. In each of the selected blocks, one word line is selected for programming. Then data is programmed using the process of FIG. 6 for all memory cells connected to the selected word line of each selected block of each plane.

One type of memory operation is a programming operation. When programming memory cells in multiple planes it is possible that a defect in one plane can cause programming of that one plane and other planes to fail. When programming fails, the block(s) of memory cells being programmed is/are retired from further use. However, if only one block in one plane is actually defective, and that one defective block causes failure of the programming process in other blocks of other planes, then prior art systems may also retire the other blocks in the other planes that also failed the programming process. This situation may result in good blocks being retired from further use, which lowers the capacity of the memory. Therefore, it is desired to determine which blocks of which planes are actually causing failure of the programming process (e.g., due to presence of a defect in that bock) and only retire those blocks actually causing failure of the programming process without retiring other good blocks. Therefore, to determine which blocks of which planes are actually causing a failure, it is proposed to concurrently programming memory cells in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to that same data state. The test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming (e.g., program voltage pulses) after completion of programming of the fastest plane to the data state. Programming is then aborted for a respective plane prior to completion of programming for all of the sub-blocks of the block in the respective plane in response to determining that any sub-block of the block in the respective plane failed programming based on the test for program failure. This concept is explained with respect to FIGS. 14A and 14B.

FIGS. 14A and 14B are tables that explain a process for verifying programming of memory cells for an embodiment that concurrently programs data into memory cells in four planes (PB0, PB1, PB2 and PB3). Each column of FIGS. 14A and 14B represents one loop (steps 604-626) of the process of FIG. 6 , including applying one program voltage pulse in step 608 and performing program-verify in step 610. Each of the rows shows which data state (see e.g., FIG. 5C) is being verified during the particular loop. In one embodiment, only one data state is being verified for a plane in any one loop. For example, in the first loop (1) the memory cells of all four planes are being verified for data state A. In loop 6, the memory cells of plane PB0 are being verified for data state C, the memory cells of plane PB1 are being verified for data state A, the memory cells of plane PB2 are being verified for data state B, and the memory cells of plane PB3 are being verified for data state B.

FIG. 14A is a table that explains an example of a process that does not employ the above-described process of using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to that same data state. In the embodiment of FIG. 14A, each plane is program-verified independently (one plane passing does not trigger a test for another plane). In the example data set, the memory cells being programmed in plane PB0 have successfully completed program-verify for data state A at loop 3 (e.g., all or enough memory cells targeted for data state A have their threshold voltage greater than VvA), the memory cells being programmed in plane PB2 have successfully completed program-verify for data state A at loop 4, and the memory cells being programmed in plane PB3 have successfully completed program-verify for data state A at loop 4. However, the block being programmed in PB1 has a defect and the memory cells of being programmed in plane PB2 do not successfully completed program-verify for data state A. As a result, the programming process does not end until loop 20 (e.g., PL=20, see step 620 of FIG. 6 ). As PB0, PB2 and PB3 completed programming by loop 12, the performance of loops 13-20 were unnecessary and wasted time (thereby reducing performance).

FIG. 14B is a table that explains an embodiment of a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state. FIG. 14A had similar data as FIG. 14B; for example, the memory cells being programmed in plane PB0 have successfully completed program-verify for data state A at loop 3, the memory cells being programmed in plane PB2 have successfully completed program-verify for data state A at loop 4, and the memory cells being programmed in plane PB3 have successfully completed program-verify for data state A at loop 4. Since PB0 successfully completed program-verify for data state A first, it triggers test for program failure of other planes to the data state A. In one embodiment, test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state A have successfully completed verification of programming for the data state A within a predetermined X doses of programming (X loops) after successfully completed verification of programming of the PB0 to data state A. The variable X can be a configurable parameter. In the example of FIG. 14B, X is set as X=4 (4 doses of programming or 4 program voltage pulses or 4 loops). At the end of four doses of programming after PB0 successfully completed program-verify for data state A, which is loop 7 in this example, the other planes are tested to see if they have successfully completed verification of programming for the data state A. If so, programming continues for those planes. If not, programming is aborted for that plane. In the example data of FIG. 14B, PB2 and PB3 successfully completed verification of programming for the data state A prior to loop 7 (i.e. in loop 4), so programming continues for those planes. However, PB1 does not successfully complete verification of programming for the data state A in loop 7; therefore, programming is aborted for PB1 at loop 7 (which is prior to completion of programming for all of the sub-blocks of the block in the PB1). The programming of the four planes depicted in FIG. 14B is stopped after loop 12, which is eight loops less than the programming of the four planes depicted in FIG. 14 a . Thus, using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state, as depicted in FIG. 14B, reduces the time used for programming, which increases performance and reduces the risk of disturb.

In the above discussion of concurrently programming data into memory cells in multiple planes, the programming process will be performed more efficiently (e.g., complete quicker) and with a lower chance of a disturb if the slower programming sub-blocks are performed earlier in the process (as per FIG. 13 ) so that a defective block will be removed from the programming process earlier in time. For example, assuming the data for FIGS. 14A and 14B show performance for one sub-block of one block in each plane, then the process of FIG. 14B will be performed five times (once for each sub-block). In that mode, if the process of FIG. 14B identifies a block that failed the test then that block is removed from programming. If the test fails at the first (or earlier programmed) sub-block for the bad block, then the time used for programming will be shorter and the risk of disturb will be less.

FIG. 15 is a flow chart describing one embodiment of a process for programming that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state and has the slower programming sub-blocks subjected to programming earlier in the process so that programming for a defective block will be stopped earlier in time. The process of FIG. 15 is an example implementation of the process of FIG. 13 . The process of FIG. 15 can be performed by any one of the one or more control circuits discussed above. For example, the process of FIG. 15 can be performed entirely by the memory die 200 (see FIG. 2A) or by the integrated memory assembly 207 (see FIG. 2B), rather than by memory controller 120. In one example, the process of FIG. 15 is performed by or at the direction of state machine 262, using other components of System Control Logic 260, Column Control Circuitry 210 and Row Control Circuitry 220. In another embodiment, the process of Figure is performed by or at the direction of memory controller 120.

In step 1502 of FIG. 15 , the speed of programming for the multiple sub-blocks relative to each other is determined. This relative speed determinations can be done on actual circuits during manufacturing and testing (e.g., testing memory die at die sort) or can be done by simulation. In one embodiment, every single block of a memory is tested and the relative speed determinations are recorded for each block. Thus, the previously determined slowest programming sub-block to fastest programming sub-block are determined separately for all blocks. In another embodiment, a generalization is made of which sub-blocks for all blocks are the slowest to fastest such that the previously determined slowest programming sub-block is a sub-block position for all blocks and the previously determined fastest programming sub-block is a sub-block position for all blocks. In some embodiments, the previously determined slowest programming sub-block is an outer sub-block (e.g., 430 and 470 of the structure of FIG. 4B) and the previously determined fastest programming sub-block is an inner sub-block (e.g., 440, 450, 460). In step 1504, the control circuit configures the previously determined slowest programming sub-block to the fastest programming sub-block from step 1502. That is, the control circuit sets a parameter that indicates speed of programming and/or order of programming among sub-blocks for every block of the memory structure. For example, FIG. 16 is a table indicating various values for that parameter. Seven bits (b6-b0) are used to configure the parameters to select one of 120 possible orders of the five sub-blocks (SB0-SB4). For example, setting b6-b0=“000000” selects the order of programming to be SB0 (slowest to program), SB4 (second slowest to program), SB1 (third slowest to program), SB3 (second fastest to program) and SB2 (fastest to program). The values of b6-b0 can be stored on the memory die (in volatile or non-volatile memory) to indicate the order from previously determined slowest programming sub-block to previously determined fastest programming sub-block, and then program in that order.

In step 1506, the control circuit concurrently programs memory cells in the multiple planes to a data state including programming data into multiple subs-blocks of blocks in the configured order of programming the multiple sub-blocks from slower sub-block to faster sub-block (e.g., as per the parameter of FIG. 16 that was set in step 1504). One embodiment of the concurrently programming of step 1506 includes using completion of programming of a fastest plane to the data state as a trigger to test for program failure of other planes to the data state, where the test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming after completion of programming of the fastest plane to the data state (step 1520), and aborting the programming for a respective plane prior to completion of programming for all of the sub-blocks of the block in the respective plane in response to determining that any sub-block of the block in the respective plane failed programming based on the test for program failure (step 1522). Steps 1520 and 1520, which implement the embodiment of FIG. 14B, can be performed for each data state being programmed to (e.g., data states A-G of FIG. 5C). The process of FIG. 15 further includes retiring from use for storing host data the block in the respective plane that failed programming based on the test for program failure (step 1508). Host data is data received from host 102 (see FIG. 1 ) or another entity external to the storage system 100.

FIG. 17 is a block diagram depicting four planes (PB0, PB1, PB2 and PB3) of memory structure 202. In other embodiments, memory structure 202 can include more or less than four planes. For example purposes, one block is depicted for each plane, including block 1750 for PB0, block 1752 for PB1, block 1754 for PB2 and block 1756 for PB3. Each block includes five sub-blocks; for example, block 1750 of PB0 includes sub-blocks SB0 (1702), SB1 (1704), SB2 (1706), SB3 (1708) and SB4 (1710); block 1752 of PB1 includes sub-blocks SB0 (1712), SB1 (1714), SB2 (1716), SB3 (1718) and SB4 (1720); block 1754 of PB2 includes sub-blocks SB0 (1722), SB1 (1724), SB2 (1726), SB3 (1728) and SB4 (1730); and block 1756 of PB3 includes sub-blocks SB0 (1732), SB1 (1734), SB2 (1736), SB3 (1738) and SB4 (1740).

Step 1506 of FIG. 15 includes concurrently programming memory cells in multiple planes. In one example, step 1506 include concurrently programming memory cells block 1750 of PB0, block 1752 of PB1, block 1754 of PB2, and block 1756 of PB3. If, in step 1504, the parameter of FIG. 16 is set such b6-b0=“000000” then the order of programming sub-blocks is SB0, SB4, SB1, SB3 and SB2, which is reflected in the table of FIG. 18 . That is, FIG. 18 is a table depicting an example order of programming when b6-b0=“000000.” Since each block includes five sub-blocks there are five phases of programming. During Phase 1, SB0 for each plane is programmed (e.g., 1702, 1712, 1722, and 1732 are scheduled to be programmed). During Phase 2, SB4 for each plane is programmed (e.g., 1710, 1720, 1730, and 1740 are scheduled to be programmed). During Phase 3, SB1 for each plane is programmed (e.g., 1704, 1714, 1724, and 1734 are scheduled to be programmed). During the Phase 4, SB3 for each plane is programmed (e.g., 1708, 1718, 1728, and 1738 are scheduled to be programmed). During Phase 5, SB2 for each plane is programmed (e.g., 1706, 1716, 1726, and 1736 are scheduled to be programmed). Each of the five phases of FIG. 18 represents the performance of steps 1520 and 1522 of FIG. 15 .

FIG. 19 is a table depicting an order of programming, show an implementation of the order of programming depicted in FIG. 18 for the process of FIG. 15 , and using the data of FIG. 14B (e.g., assume PB1 has a defect in sub-block 1712). The programming of Phase 1 completes successfully for sub-blocks 1702, 1722 and 1732; however, sub-block 1712 of block 1752 never successfully verifies for data state A (as per FIG. 14B) and, thus, fails programming as per step 1520. As a result, programming is aborted for block 1752 (see step 1522), sub-blocks 1720/1714/1718/1716 are not programmed and block 1752 is retired from use for storing host data (see step 1508). Since block 17652 failed programming, the data will be programmed to a different block.

A non-volatile memory has been introduced that performs memory operations faster due to an optimized order of performance.

One embodiment includes a non-volatile storage apparatus, comprising: a first group of non-volatile memory cells divided into portions of the first group, each portion of the first group can be independently programmed without programming other portions of the first group; and a control circuit connected to the memory cells, the control circuit is configured to separately perform a memory operation for multiple portions of the first group in order from previously determined slowest portion of the first group to previously determined faster portions of the first group.

In one example implementation, the control circuit is configured to separately program multiple portions of the first group in order from a previously determined slowest programming portion of the first group to previously determined faster portions of the first group.

In one example implementation, the control circuit is configured to separately program multiple portions of the first group in order from previously determined slowest programming portion of the first group to previously determined fastest portion of the first group; the first group is a block of non-volatile memory cells; the previously determined slowest programming portion of the first group is an outer sub-block; and the previously determined fastest portion of the first group in an inner sub-block.

In one example implementation, the first group is a block of non-volatile memory cells arranged as NAND strings; the portions of the first group are sub-blocks of the block; each of the sub-blocks include a subset of the NAND strings such that each of the NAND strings is positioned in only one of the sub-blocks; the previously determined slowest programming portion of the group is an outer sub-block; and the previously determined faster portion of the group in an inner sub-block.

One example implementation further includes a memory structure. The memory structure comprises multiple planes, each plane comprising multiple groups of non-volatile memory cells divided into portions for each group, each portion of each group can be independently programmed without programming other portions of a same group, the control circuit is connected to the memory structure, the control circuit is configured to concurrently program memory cells in the multiple planes to a data state including using completion of programming of a fastest plane to the data state as a trigger to test for program failure of other planes to the data state, the test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming after completion of programming of the fastest plane to the data state, the control circuit is configured to concurrently program memory cells in the multiple planes to a data state by programming each portion of a group in each plane in order from previously determined slowest programming portion to previously determined faster programming portion and aborting the programming for the respective plane prior to completion of programming for all of the portions of the group in the respective plane in response to determining that any portion of the group in the respective plane failed programming based on the test for program failure.

One example implementation further includes a memory structure. The memory structure, the memory structure comprises multiple planes, each plane comprising multiple blocks of non-volatile memory cells divided into sub-blocks, each sub-block of each block can be independently programmed without programming other sub-blocks of a same block, the control circuit is connected to the memory structure, the control circuit is configured to concurrently program memory cells in the multiple planes to a data state including using completion of programming of a fastest plane to the data state as a trigger to test for program failure of other planes to the data state, the test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming after completion of programming of the fastest plane to the data state, the control circuit is configured to concurrently program memory cells in the multiple planes to a data state by programming each sub-block of a block in each plane in order from previously determined slowest programming sub-block to previously determined fastest programming sub-block and aborting the programming for the respective plane prior to completion of programming for all of the sub-blocks of the block in the respective plane in response to determining that any sub-block of the block in the respective plane failed programming based on the test for program failure.

In one example implementation, the doses of programming are voltage pulses.

In one example implementation, the previously determined slowest programming sub-block is an outer sub-block; and the previously determined fastest programming sub-block is an inner sub-block.

In one example implementation, the previously determined slowest programming sub-block is a sub-block position for all blocks.

In one example implementation, the previously determined slowest programming sub-block is determined separately for all blocks.

In one example implementation, the control circuit is configured to retire from use for storing host data the block in the respective plane that failed programming based on the test for program failure.

In one example implementation, the control circuit is configured to check a parameter that indicates the order from previously determined slowest programming sub-block to previously determined fastest programming sub-block.

One embodiment includes a method for operating non-volatile memory cells of a memory structure, the memory structure is implemented as multiple planes of non-volatile memory cells, each plane comprises multiple blocks of non-volatile memory cells, each block comprises multiple sub-blocks, and each sub-block comprises multiple non-volatile memory cells. The method comprises: determining speed of programming for the multiple sub-blocks relative to each other; configuring order of programming the multiple sub-blocks from slower programming sub-block to faster programming sub-block; and concurrently programming memory cells in the multiple planes to a data state including programming data into multiple subs-blocks of blocks in the configured order of programming the multiple sub-blocks from slower programming sub-block to faster programming sub-block.

In one example implementation, the concurrently programming memory cells in the multiple planes to the data state includes: using completion of programming of a fastest plane to the data state as a trigger to test for program failure of other planes to the data state, the test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming after completion of programming of the fastest plane to the data state. Additionally, the concurrently programming memory cells in the multiple planes to the data state further includes: aborting the programming for a respective plane prior to completion of programming for all of the sub-blocks of the block in the respective plane in response to determining that any sub-block of the block in the respective plane failed programming based on the test for program failure.

In one example implementation, the determining speed of programming for the multiple sub-blocks relative to each other comprises testing memory die at die sort.

In one example implementation, the configuring order of programming comprises setting a parameter for the non-volatile memory cells that indicates order of programming among sub-blocks for every block of the memory structure.

One embodiment includes a non-volatile storage apparatus that comprises non-volatile memory cells arranged in a memory structure and a control circuit connected to the memory structure. The memory structure comprises multiple planes, each plane comprising multiple blocks, each block comprising multiple sub-blocks, and each sub-block of a block can be independently programmed without programming other sub-blocks of the block. The control circuit is configured to concurrently program memory cells in the multiple planes to a data state including using completion of programming of a fastest plane to the data state as a trigger to test for program failure of other planes to the data state, the test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming after completion of programming of the fastest plane to the data state, the control circuit is configured to concurrently program memory cells in the multiple planes to the data state by programming each sub-block of a block in each plane in order from previously determined slowest erasing sub-block to previously determined fastest erasing sub-block and aborting the programming for the respective plane prior to completion of programming for all of the sub-blocks of the block in the respective plane in response to determining that any sub-block of the block in the respective plane failed programming based on the test for program failure. In one example implementation, the previously determined slowest programming sub-block is an outer sub-block and the previously determined fastest programming sub-block is an inner sub-block.

For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.

For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.

For purposes of this document, the term “based on” may be read as “based at least in part on.”

For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.

For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto. 

What is claimed is:
 1. A non-volatile storage apparatus, comprising: a first group of non-volatile memory cells divided into portions of the first group, each portion of the first group can be independently programmed without programming other portions of the first group; and a control circuit connected to the memory cells, the control circuit is configured to separately perform a memory operation for multiple portions of the first group in order from previously determined slowest portion of the first group to previously determined faster portions of the first group.
 2. The non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to separately program multiple portions of the first group in order from a previously determined slowest programming portion of the first group to previously determined faster portions of the first group.
 3. The non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to separately program multiple portions of the first group in order from previously determined slowest programming portion of the first group to previously determined fastest portion of the first group.
 4. The non-volatile storage apparatus of claim 3, wherein: the first group is a block of non-volatile memory cells; the previously determined slowest programming portion of the first group is an outer sub-block; and the previously determined fastest portion of the first group in an inner sub-block.
 5. The non-volatile storage apparatus of claim 1, wherein: the first group is a block of non-volatile memory cells arranged as NAND strings; the portions of the first group are sub-blocks of the block; each of the sub-blocks include a subset of the NAND strings such that each of the NAND strings is positioned in only one of the sub-blocks; the previously determined slowest programming portion of the group is an outer sub-block; and the previously determined faster portion of the group in an inner sub-block.
 6. The non-volatile storage apparatus of claim 1, further comprising: a memory structure, the memory structure comprises multiple planes, each plane comprising multiple groups of non-volatile memory cells divided into portions for each group, each portion of each group can be independently programmed without programming other portions of a same group, the control circuit is connected to the memory structure, the control circuit is configured to concurrently program memory cells in the multiple planes to a data state including using completion of programming of a fastest plane to the data state as a trigger to test for program failure of other planes to the data state, the test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming after completion of programming of the fastest plane to the data state, the control circuit is configured to concurrently program memory cells in the multiple planes to a data state by programming each portion of a group in each plane in order from previously determined slowest programming portion to previously determined faster programming portion and aborting the programming for the respective plane prior to completion of programming for all of the portions of the group in the respective plane in response to determining that any portion of the group in the respective plane failed programming based on the test for program failure.
 7. The non-volatile storage apparatus of claim 1, further comprising: a memory structure, the memory structure comprises multiple planes, each plane comprising multiple blocks of non-volatile memory cells divided into sub-blocks, each sub-block of each block can be independently programmed without programming other sub-blocks of a same block, the control circuit is connected to the memory structure, the control circuit is configured to concurrently program memory cells in the multiple planes to a data state including using completion of programming of a fastest plane to the data state as a trigger to test for program failure of other planes to the data state, the test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming after completion of programming of the fastest plane to the data state, the control circuit is configured to concurrently program memory cells in the multiple planes to a data state by programming each sub-block of a block in each plane in order from previously determined slowest programming sub-block to previously determined fastest programming sub-block and aborting the programming for the respective plane prior to completion of programming for all of the sub-blocks of the block in the respective plane in response to determining that any sub-block of the block in the respective plane failed programming based on the test for program failure.
 8. The non-volatile storage apparatus of claim 7, wherein: the doses of programming are voltage pulses.
 9. The non-volatile storage apparatus of claim 7, wherein: the previously determined slowest programming sub-block is an outer sub-block; and the previously determined fastest programming sub-block is an inner sub-block.
 10. The non-volatile storage apparatus of claim 7, wherein: the previously determined slowest programming sub-block is a sub-block position for all blocks.
 11. The non-volatile storage apparatus of claim 7, wherein: the previously determined slowest programming sub-block is determined separately for all blocks.
 12. The non-volatile storage apparatus of claim 7, wherein: the control circuit is configured to retire from use for storing host data the block in the respective plane that failed programming based on the test for program failure.
 13. The non-volatile storage apparatus of claim 7, wherein: the control circuit is configured to check a parameter that indicates the order from previously determined slowest programming sub-block to previously determined fastest programming sub-block.
 14. A method for operating non-volatile memory cells of a memory structure, the memory structure is implemented as multiple planes of non-volatile memory cells, each plane comprises multiple blocks of non-volatile memory cells, each block comprises multiple sub-blocks, each sub-block comprises multiple non-volatile memory cells, the method comprising: determining speed of programming for the multiple sub-blocks relative to each other; configuring order of programming the multiple sub-blocks from slower programming sub-block to faster programming sub-block; and concurrently programming memory cells in the multiple planes to a data state including programming data into multiple subs-blocks of blocks in the configured order of programming the multiple sub-blocks from slower programming sub-block to faster programming sub-block.
 15. The method of claim 14, wherein the concurrently programming memory cells in the multiple planes to the data state includes: using completion of programming of a fastest plane to the data state as a trigger to test for program failure of other planes to the data state, the test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming after completion of programming of the fastest plane to the data state.
 16. The method of claim 15, wherein the concurrently programming memory cells in the multiple planes to the data state further includes: aborting the programming for a respective plane prior to completion of programming for all of the sub-blocks of the block in the respective plane in response to determining that any sub-block of the block in the respective plane failed programming based on the test for program failure.
 17. The method of claim 14, wherein: the determining speed of programming for the multiple sub-blocks relative to each other comprises testing memory die at die sort.
 18. The method of claim 14, wherein: the configuring order of programming comprises setting a parameter for the non-volatile memory cells that indicates order of programming among sub-blocks for every block of the memory structure.
 19. A non-volatile storage apparatus, comprising: non-volatile memory cells arranged in a memory structure, the memory structure comprising multiple planes, each plane comprising multiple blocks, each block comprising multiple sub-blocks, each sub-block of a block can be independently programmed without programming other sub-blocks of the block; and a control circuit connected to the memory structure, the control circuit is configured to concurrently program memory cells in the multiple planes to a data state including using completion of programming of a fastest plane to the data state as a trigger to test for program failure of other planes to the data state, the test for program failure of other planes to the data state comprises determining if the memory cells of the other planes that are targeted for programming to the data state have successfully completed verification of programming for the data state within a predetermined number of doses of programming after completion of programming of the fastest plane to the data state, the control circuit is configured to concurrently program memory cells in the multiple planes to the data state by programming each sub-block of a block in each plane in order from previously determined slowest erasing sub-block to previously determined fastest erasing sub-block and aborting the programming for the respective plane prior to completion of programming for all of the sub-blocks of the block in the respective plane in response to determining that any sub-block of the block in the respective plane failed programming based on the test for program failure.
 20. The non-volatile storage apparatus of claim 19, wherein: the previously determined slowest programming sub-block is an outer sub-block; and the previously determined fastest programming sub-block is an inner sub-block. 